As is well-known in the art, complementary metal oxide semiconductor (CMOS) technology can provide important advantages relative to P-type metal oxide semiconductor (PMOS) or N-type metal oxide semiconductor (NMOS) technologies. In particular, CMOS circuits typically draw much less steady-state current than PMOS-only or NMOS-only circuits, and therefore provide much greater power efficiency. An example of the superior power efficiency of CMOS circuits is illustrated in connection with FIGS. 1A through 1C, which depict conventional inverter circuits (also referred to as “NOT” logic gates). As seen in FIG. 1A, an NMOS inverter 10 includes a first NMOS transistor 12 and a second NMOS transistor 14. NMOS transistor 12 is configured as a “pull-up resistor” by shorting the gate to the drain, while NMOS transistor 14 functions as an active switching element. When the input voltage vi changes to a “high” state, NMOS transistor 14 turns on (i.e., has a conducting channel), and NMOS inverter 10 draws current through both NMOS transistors 12, 14. This provides a “low” state at the output voltage v0, but dissipates power in the resistive element (NMOS transistor 12). The current and power dissipation subsist until the input voltage vi changes to a “low” state, which causes NMOS transistor 14 to turn off (i.e., have a non-conducting channel). Similarly in FIG. 1B, a PMOS inverter 20 includes a first PMOS transistor 22 and a second PMOS transistor 24. PMOS transistor 22 is configured as a “pull-down resistor” by shorting the gate to the source, while PMOS transistor 24 functions as an active switching element. When the input voltage vi changes to a “low” state, PMOS transistor 24 turns on, and PMOS inverter 20 draws current through both PMOS transistors 22, 24. This provides a “high” state at the output voltage v0, but dissipates power in the resistive element (PMOS transistor 22). The current and power dissipation subsist until the input voltage vi changes to a “high” state, which causes PMOS transistor 24 to turn off. In both inverters 10, 20, therefore, a relatively large amount of power is dissipated even in a steady-state condition.
By combining NMOS and PMOS active switching elements, and removing passive elements, one can avoid the steady-state current drain, and relatively large power dissipation, associated with inverters 10, 20. As seen in FIG. 1C, a CMOS inverter 30 includes a PMOS transistor 32 and an NMOS transistor 34, both of which are configured as active switching elements. The gates of both transistors 32, 34 are electrically coupled together and accept the input voltage v7, and the source of PMOS transistor 32 is electrically coupled to the drain of NMOS transistor 34. When the input voltage vi changes to a “low” state, PMOS transistor 32 is turned on, but NMOS transistor 34 is turned off. When the input voltage vi changes to a “high” state, NMOS transistor 34 is turned on, but PMOS transistor 34 is turned off. Thus, CMOS inverter 30 only completes a conduction path for current between the power supply and ground during a brief time when the input voltage vi is changing from high to low, or vice versa. The lack of steady-state current can dramatically decrease power dissipation, and improve reliability, relative to inverters 10, 20. Moreover, the two actively switching elements of CMOS inverter 30 provide a balanced configuration, which generally permits higher switching speeds as compared to inverters 10, 20. Conversely, for inverters 10, 20, the resistance of the passive component (i.e., NMOS transistor 12 in FIG. 1A and PMOS transistor 22 in FIG. 1B) can interact with circuit capacitance to cause switching delays. In particular, switching the input voltage vi from high to low causes slower switching in NMOS inverter 10, and switching the input voltage vi from low to high causes slower switching in PMOS inverter 20. In addition to the CMOS inverter 30 of FIG. 1C, CMOS technology can provide improvements of this sort for other circuit configurations, such as a logical “NAND” gate configuration.
Due to these benefits, CMOS technology is widely used in different types of digital electronic circuit applications. Moreover, similar complementary circuit topologies are used in connection with other, non-MOS transistor technologies. One transistor technology to which the benefits of complementary circuits can be applied is that of organic thin film transistors (OTFTs). OTFTs are thin film transistors (TFTs) that use an organic material (e.g., small-molecule or polymeric semiconductors) for the N-type or P-type channel. Recent progress has been made with regard to integrating both N-type and P-type OTFTs on a single substrate to form a complementary arrangement (C-OTFT), such as the arrangement of the CMOS inverter 30 in FIG. 1C, for example. To date, this has been performed by processing N-type OTFTs and P-type OTFTs sequentially on the single substrate, and forming the appropriate electrical connections.
Both additive methods (e.g., printing) and subtractive methods (e.g., photolithography) have been used to fabricate C-OTFT circuits. When using additive methods, the P-type or N-type material is typically deposited only where needed. This approach is used in the emerging field of printed electronics, for example. When using subtractive methods, the P-type or N-type material is deposited over a large area (e.g., over the entire substrate), and subsequently removed everywhere except for those locations where the material is desired. This approach is used in conventional semiconductor and display processing facilities, for example.
Unfortunately, the processing steps involved in these additive and subtractive methods can give rise to various problems that cause lower yields, increased production costs and/or degraded performance of the C-OTFT circuits. FIG. 2A shows a stack 40 that may be built and used, along with the appropriate electrical connections, to form a C-OTFT circuit. In FIG. 2A (and throughout the figures), “P-OSC” refers to P-type organic semiconductor material for the P-type transistor channel, and “N-OSC” refers to N-type organic semiconductor material for the N-type transistor channel. While low-cost, high-throughput additive methods such as printing can be used to build stack 40, the process is complicated by the fact that all layers generally need to be compatible with both P-type and N-type OTFTs. Among other possible drawbacks, this restriction may limit the choice of materials, require performance tradeoffs, and/or increase cost. Alternatively, N-type and P-type OTFT stacks may be processed one on top of the other on the single substrate. With either technique, however, the monolithic integration of the N-type and P-type OTFT stacks on a single substrate causes complexities that will generally lower yields, degrade performance, limit the choice of materials, and/or increase costs. As one example, monolithic integration creates a “weakest link” situation, where a low-yield process for fabricating P-type OTFTs will result in an low overall yield for C-OTFT circuits even if the process for fabricating N-type OTFTs is high-yield, and vice versa.
Problems also arise when fabricating stack 40 using subtractive methods. For example, photolithography typically degrades the performance of both the N-type and P-type OTFTs within the C-OTFT circuit. In particular, the semiconductor materials that are applied first (e.g., for the P-type OTFTs) are degraded by the subsequent wet processing steps used to apply and pattern the remaining semiconductor materials (e.g., for the N-type OTFTs). Further, the processing needed to apply and selectively remove the first semiconductor layer (e.g., either the P-OSC or the N-OSC) typically results in contamination of the channel of the second semiconductor layer of the other polarity. In an attempt to avoid these problems, some recent techniques have instead processed the materials for the N-type and P-type OTFTs on different layers supported by the single substrate. Two such techniques are illustrated in FIGS. 2B and 2C. As seen in FIG. 2B, a stack 50 can be fabricated in which the N-type and P-type OTFT stacks are built one over the other on the substrate, with a single metal layer serving as both the gate of the P-type OTFTs and the source and drain of the N-type OTFTs. Alternatively, as seen in FIG. 2C, a stack 60 can be fabricated in which the N-type and P-type OTFT stacks share a single dielectric layer, with the gate of the P-type OTFT on the bottom and the gate of the N-type OTFT on the top (or vice versa). As with the stack 40, however, the stacks 50, 60 require monolithic integration of P-type and N-type OTFTs on a single substrate. As noted above, the complexity of monolithic integration generally leads to lower yields, degraded performance, limited choice of materials, and/or increased costs.
Despite these challenges, C-OTFT technology holds great potential for various different applications. One emerging area in which C-OTFT technology is well-suited for use is that of flexible displays. More generally, complementary circuit topologies have several potential applications within electronic displays. For example, complementary circuits may be used to form display driver circuits (i.e., circuits that drive the pixel circuits of the display) that are integrated on the backplane of the display using the same transistor technology as the pixel circuits. A typical pixel circuit 80 is shown in FIG. 3. The pixel circuit 80 includes only a single TFT 82, which can be either N-type or P-type, as well as various capacitors. The pixel circuit 80 may be used with active-matrix liquid crystal displays (LCDs), electronic paper displays (EPDs), electrowetting displays, and other display technologies. Complementary circuit topologies may be used within the driver to form a shift register (for the gate direction), a multiplexer circuit (for the gate and/or source direction), or a complete source driver, for example. Complementary circuits may even be used as a part of the display controller, and/or other electronics required for a product. Because each of these applications uses digital complementary circuits (e.g., including logic gates such as the inverter 30 of FIG. 1C), a huge decrease in power consumption may be obtained relative to non-complementary circuits (e.g., by roughly a factor of 300), as well as improved circuit reliability.
Complementary circuits may also be used in memory displays. This is a relatively recent development in which each pixel is associated with its own memory to store a grey level state. Because each pixel remembers its grey level state, there is no need to drive the pixel until that pixel changes to a different grey level state. As a result, the gate and source lines do not need to be driven continuously, and power consumption may be greatly reduced.
In yet another application, complementary circuits may be used for certain organic light-emitting diode (OLED) displays. Whereas complex circuitry is typically required to maintain a constant current across different grey levels of an OLED display over its lifetime, a complementary arrangement can reduce that complexity, reduce power consumption, and decrease the number of required signal lines per pixel.